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| November 2006 rev 1.5 3.3V Zero Delay Buffer Features * ASM5P2304A the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500pS. The ASM5P2304A is available in two different Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P2304A Configurations Table". Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. * * * * * * Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. * Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. * configurations (Refer "ASM5P2304A Configurations Table). The ASM5P2304A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P2304A-2 allows the user to obtain REF and 1/2X or 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. * * * Functional Description ASM5P2304A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in 8 pin package. The part has an on-chip PLL which locks to an input clock presented on Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 1.5 ASM5P2304A Configurations Device ASM5P2304A-1 ASM5P2304A-1H ASM5P2304A-2 ASM5P2304A-2 ASM5P2304A-2H ASM5P2304A-2H ASM5P2304A Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference 2 X Reference Bank B Frequency Reference Reference Reference /2 Reference Reference/2 Reference Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1500 1000 REF-Input to CLKA / CLKB Delay (pS) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 14 November 2006 rev 1.5 Pin Configuration REF 1 CLKA1 2 CLKA2 3 GND 4 ASM5P2304A 8 FBK 7 VDD 6 CLKB2 5 CLKB1 ASM5P2304A Pin Description for ASM5P2304A Pin # 1 2 3 4 5 6 7 8 Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 14 November 2006 rev 1.5 Absolute Maximum Ratings ASM5P2304A Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 Unit V V V C C C 2000 V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P2304A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V C pF pF pF Operating Temperature (Ambient Temperature) Load Capacitance, from 15MHz to 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance3 Note: 3. Applies to both Ref Clock and FBK. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 14 November 2006 rev 1.5 Electrical Characteristics for ASM5P2304A Commercial Temperature Devices ASM5P2304A Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 50.0 100.0 A A VOL Output LOW Voltage 4 0.4 V VOH Output HIGH Voltage 4 2.4 V 45.0 IDD Supply Current Unloaded outputs, 66MHz REF (-1, -1H, -2, -2H) Unloaded outputs, 33MHz REF (-1, -1H, -2, -2H) 32.0 mA 18.0 Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 14 November 2006 rev 1.5 Switching Characteristics for ASM5P2304A Commercial Temperature Devices Parameter 1/t1 1/t1 ASM5P2304A Description Output Frequency Output Frequency Duty Cycle5= (t2 / t1) * 100 (-1, -2, -1H, -2H) Duty Cycle5 = (t2 / t1) * 100 (-1, -2,-1H, -2H) Test Conditions 30pF load, -1H, -2H devices 15pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66MHz 30pF load Measured at 1.4V, FOUT = <50MHz 15 pF load Measured between 0.8V and 2.0V 30pF load Measured between 0.8V and 2.0V 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 2.0V and 0.8V 30pF load Measured between 2.0V and 0.8V 15pF load Measured between 2.0V and 0.8V 30pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded 5 Min 15 15 40.0 Typ Max 133 133 Unit MHz MHz % 50.0 60.0 45.0 50.0 55.0 % t3 Output Rise Time5 (-1, -2) Output Rise Time5 (-1, -2) Output Rise Time5 (-1H, -2H) Output Fall Time 5 (-1, -2) Output Fall Time 5 (-1, -2) Output Fall Time5 (-1H, -2H) Output-to-output skew on same bank (-1, -2)5 Output-to-output skew (-1H, -2H) 2.20 nS t3 1.50 nS t3 1.50 nS t4 2.20 nS t4 1.50 nS t4 1.25 200 200 nS t5 pS Output bank A -to- output bank B skew (-1, -2H) Output bank A to output Bank B skew (-2) 200 400 0 0 1 250 500 pS pS V/nS t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge Device-to-Device Skew5 Output Slew Rate5 Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15pF load 175 pS tJ Cycle-to-cycle jitter 5 (-1, -1H, -2H) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 25MHz, loaded outputs, 15pF load 200 100 400 pS 375 tJ Cycle-to-cycle jitter 5 (-2) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 66.67MHz, loaded outputs, 15pF load Stable power supply, valid clock presented on REF and FBK pins tLOCK PLL Lock Time 5 1.0 mS Note: 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 14 November 2006 rev 1.5 Operating Conditions for ASM5I2304A Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, from 15MHz to 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance6 ASM5P2304A Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF Note: 6. Applies to both Ref Clock and FBK. Electrical Characteristics for ASM5I2304A Industrial Temperature Devices Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 50.0 100.0 A A VOL Output LOW Voltage 7 0.4 V VOH Output HIGH Voltage 7 2.4 V 45.0 IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) 35.0 mA 20.0 Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 14 November 2006 rev 1.5 Switching Characteristics for ASM5I2304A Industrial Temperature Devices All parameters are specified with loaded outputs ASM5P2304A Parameter 1/t1 1/t1 Description Output Frequency Output Frequency Duty Cycle8 = (t2 / t1) * 100 (-1, -2, -1H, -2H) Duty Cycle8= (t2 / t1) * 100 (-1, -2, -1H, -2H) Test Conditions 30pF load, -1H, -2H devices 15pF load, -1 and -2 devices Measured at 1.4V, FOUT = <66.66MHz 30pF load Measured at 1.4V, FOUT = <50 MHz 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 0.8V and 2.0V 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 2.0V and 0.8V 30pF load Measured between 2.0V and 0.8V 15pF load Measured between 2.0V and 0.8V 30pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded 8 Min 15 15 40.0 Typ Max 133 133 Unit MHz MHz % 50.0 60.0 45.0 50.0 55.0 % t3 Output Rise Time8 (-1, -2) Output Rise Time8 (-1, -2) Output Rise Time8 (-1H, -2H) Output Fall Time8 (-1, -2) Output Fall Time8 (-1, -2) Output Fall Time8 (-1H, -2H) Output-to-output skew on same bank (-1, -2)8 Output-to-output skew (-1H, -2H) Output bank A -to- output bank B skew (-1, -2H) Output bank A -to- output bank B skew (-2) 2.50 nS t3 1.50 nS t3 1.50 nS t4 2.50 nS t4 1.50 nS t4 1.25 200 200 200 400 0 0 250 500 nS t5 pS t6 t7 Delay, REF Rising Edge to FBK Rising Edge Device-to-Device Skew8 Output Slew Rate8 Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15pF load 1 pS pS t8 V/nS 180 pS tJ Cycle-to-cycle jitter 8 (-1, -1H, -2H) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 25MHz, loaded outputs, 15pF load Measured at 66.67MHz, loaded outputs, 30pF load Measured at 66.67MHz, loaded outputs, 15pF load 200 100 tJ Cycle-to-cycle jitter8 (-2) 400 pS 380 tLOCK PLL Lock Time8 Stable power supply, valid clock presented on REF and FBK pins 1.0 mS Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 14 November 2006 rev 1.5 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V ASM5P2304A All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V Output - Output Skew 1.4 V OUTPUT1 1.4 V OUTPUT2 t 5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew VDD /2 CLKOUT, Device 1 CLKOUT, Device 2 t VDD /2 7 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 14 November 2006 rev 1.5 Test Circuits ASM5P2304A TEST CIRCUIT #1 +3.3V VDD 0.1uF GND OUTPUT CLKOUT CLOAD TEST CIRCUIT # 2 1K OUTPUT 1K CLKOUT CLOAD 10pF +3.3V VDD 0.1uF GND For parameter t8 (output skew rate) on -1H devices 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 14 November 2006 rev 1.5 Package Information 8-lead (150-mil) SOIC Package ASM5P2304A E H D A2 A e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 14 November 2006 rev 1.5 Ordering Codes Ordering Code ASM5P2304AF-1-08-SR ASM5P2304AF-1-08-ST ASM5I2304AF-1-08-SR ASM5I2304AF-1-08-ST ASM5P2304AF-1H-08-SR ASM5P2304AF-1H-08-ST ASM5I2304AF-1H-08-SR ASM5I2304AF-1H-08-ST ASM5P2304AF-2-08-SR ASM5P2304AF-2-08-ST ASM5I2304AF-2-08-SR ASM5I2304AF-2-08-ST ASM5P2304AF-2H-08-SR ASM5P2304AF-2H-08-ST ASM5I2304AF-2H-08-SR ASM5I2304AF-2H-08-ST ASM5P2304AG-1-08-SR ASM5P2304AG-1-08-ST ASM5I2304AG-1-08-SR ASM5I2304AG-1-08-ST ASM5P2304AG-1H-08-SR ASM5P2304AG-1H-08-ST ASM5I2304AG-1H-08-SR ASM5I2304AG-1H-08-ST ASM5P2304AG-2-08-SR ASM5P2304AG-2-08-ST ASM5I2304AG-2-08-SR ASM5I2304AG-2-08-ST ASM5P2304AG-2H-08-SR ASM5P2304AG-2H-08-ST ASM5I2304AG-2H-08-SR ASM5I2304AG-2H-08-ST ASM5P2304A Marking 5P2304AF-1 5P2304AF-1 5I2304AF-1 5I2304AF-1 5P2304AF-1H 5P2304AF-1H 5I2304AF-1H 5I2304AF-1H 5P2304AF-2 5P2304AF-2 5I2304AF-2 5I2304AF-2 5P2304AF-2H 5P2304AF-2H 5I2304AF-2H 5I2304AF-2H 5P2304AG-1 5P2304AG-1 5I2304AG-1 5I2304AG-1 5P2304AG-1H 5P2304AG-1H 5I2304AG-1H 5I2304AG-1H 5P2304AG-2 5P2304AG-2 5I2304AG-2 5I2304AG-2 5P2304AG-2H 5P2304AG-2H 5I2304AG-2H 5I2304AG-2H Package Type 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green Temperature Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 14 November 2006 rev 1.5 Device Ordering Information ASM5P2304A ASM5P2304AF-08-SR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 14 November 2006 rev 1.5 ASM5P2304A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: ASM5P2304A Document Version: 1.5 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 (c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 14 |
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